Performance Evaluation on a Micro-threading Pipeline

Luo, B. and Jesshope, C.

The micro-threaded microprocessor is a chip multi-processor, which uses a multi-threaded approach, where the threads are obtained from within a single context and exploit both vector and instruction level parallelism (ILP). This approach employs vertical and horizontal transfer in a simple pipeline. The horizontal transfer is referred to as the normal scalar pipeline processing used in most microprocessors. Vertical transfer is a context switch, which allows the code to tolerate any latency from undetermined data and control dependencies. The performance of the single pipeline is very important in the overall performance of the whole processor, which can distribute threads to any of the available processors. We have measured the influence of three crucial parameters - cache delay, cache miss rate, and number of registers - on the performance using our simulator. Even for a long cache delay (1000 processor cycles) we found that the micro-threaded pipeline can still achieves an IPC of 0.8 in the peak performance which is some 6 times better than a conventional scalar pipeline. If we further degrade cache performance by using an artificially small cache line size the performance of conventional scalar pipeline gives an IPC of 0.02, whereas with unlimited registers the micro-threaded pipeline still manages to achieve and IPC of 0.8 (a factor of 40 difference in performance).

Cite as: Luo, B. and Jesshope, C. (2002). Performance Evaluation on a Micro-threading Pipeline. In Proc. Seventh Asia-Pacific Computer Systems Architectures Conference (ACSAC2002), Melbourne, Australia. CRPIT, 6. Lai, F. and Morris, J., Eds. ACS. 83-90.

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