Sentry Tag: An Efficient Filter Scheme for Low Power Cache

Chang, Y.-J., Ruan, S.-J. and Lai, F.

In this paper, we focus on low power design at the architecture level and propose a new architecture, called sentry tag, for reducing the on-chip cache power consumption in processors. The many unnecessary activities in the conventional cache-access process motivate our proposal. By pre-comparing the sentry bit of the access address with the sentry tag before starting a normal cache access, we can filter out and eliminate most unnecessary activities. Thus the power consumption can be effectively reduced. Our method is valuable for both a conventional cache with parallel access and a phased cache with serial access. We used SimpleScalar, a trace-driven simulator, to evaluate the performance of our proposed architecture. Compared to a conventional cache, experimental results from SPEC95 benchmarks show that the additional sentry tag can reduce many unnecessary activities (and hence the power consumption), while the hardware overhead is insignificant. For example, an 8-KB, 4-way data cache with two-bit sentry tag can improve the power consumption by 35% compared to a conventional set-associative cache. The maximum power saving achieved using this architecture depends on the cache configuration, which suggests that the proposed sentry tag is a viable choice for data caches with higher associativity.

Cite as: Chang, Y.-J., Ruan, S.-J. and Lai, F. (2002). Sentry Tag: An Efficient Filter Scheme for Low Power Cache. In Proc. Seventh Asia-Pacific Computer Systems Architectures Conference (ACSAC2002), Melbourne, Australia. CRPIT, 6. Lai, F. and Morris, J., Eds. ACS. 135-140.

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