Hardware Trojan Resistant Computation using Heterogeneous COTS Processors

Beaumont, M., Hopkins, B. and Newby, T.

Hardware Trojans pose a credible and increasing threat to computer security, with the potential to compromise the very electronics that ostensibly provide the security primitives underpinning various computer architectures. The discovery of stealthy Hardware Trojans within Integrated Circuits by current state-of-the-art pre- and post-manufacturing test and verification techniques cannot be guaranteed. Therefore electronic systems, especially those controlling safety or security critical systems should be designed to operate with integrity in the presence of any Hardware Trojans, and regardless of any Trojan activity. We present an architecture that fragments and replicates computation over a pool of Commercial-Off-The-Shelf processors with widely heterogeneous architectures. Processors are loosely synchronised through their use of a voted, architecture-independent message box mechanism to access a common memory space. A minimal Trusted Computing Base abstracts the processors as a single computational entity that can tolerate the effects of arbitrary Hardware Trojans within individual processors. The architecture provides integrity, data confidentiality, and availability for executing applications.

Cite as: Beaumont, M., Hopkins, B. and Newby, T. (2013). Hardware Trojan Resistant Computation using Heterogeneous COTS Processors. In Proc. Computer Science 2013 (ACSC 2013) Adelaide, Australia. CRPIT, 135. Thomas, B. Eds., ACS. 97 - 106

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